Section: New Results

Correct and efficient implementation of polychronous formalisms

Participants : Thomas Carle, Manel Djemal, Virginia Papailiopoulou, Dumitru Potop Butucaru, Robert de Simone, Yves Sorel.

Existing analysis techniques for synchronous and polychronous languages, such as clock calculi, are meant to extract relations of simultaneity (time inclusion) and exclusiveness (time exclusion) between the various computations and communications. This approach is well-suited when targeting sequential processors. For distributed or multi-threaded implementations, further independence relations are needed to express potential concurrency. This resulted in a general theory of endochronous systems, meant to support this additional analysis [11] .

Last year we completed a first prototype tool implementation for weak endochrony checking. This was completed this year in two directions:

• connecting our tool with Signal as input language, and interface it in practice to the Polychrony/SME environment developed by the Espresso EPI;

• Improving algorithmic complexity and internal data representaion, so that our tool can now handle reasonable size Signal programs.

This work was of course conducted in collaboration with Espresso members. Experimental results were presented at the ESLsyn 2011 conference [30] . We are currently expanding the framework in orer to take modes/states into account in the program specifications. Effective generation of multi-threaded GALS wrappers for Signal programs is also under way.

We worked at extending the AAA methodology for polychronous processes by providing a better integration of clock analysis in the various phases of the implementation process (allocation, scheduling, pipelining, etc.). We also considered a wider range of implementation targets (time-triggered, MPSoC). We defined a dedicated software pipelining algorithm to match conditional scheduling/reservation tables such as used in SynDEx, with the goal of improving throughput with the same duration of individual computation cycles (as is the goal of any pipelning techniques). The originality here is to make logical clocks of polychronous systems act as triggers for the predicated executions as used in traditional software pipelining. First results have been presented during the Synchron 2011 workshop and in a research report [41] .

Further work on time-triggered systems was submitted inside the FUI Parsec 8.2.4 and P 8.2.5 projects, including real-time implementation methods for the IMA/ARINC 653 avionics platforms. In particular we conducted experiments to replace the scheduling policy of the second-level scheduler (L1 in the standard) from dynamic priority-driven to dynamic Time Division time triggered (TT-IMA). Preliminary results are under way, and were informally presented at the yearly Synchron seminar.

An important emerging trend in target MPSoC platforms is that On-chip networks are progressively introduced to cope with the botleneck of iter processor communications. Correct implementation of polychronous systems in this context thus relies on efficient routing of data in such networks, and ultimately may assume that on-chip NoC routers may be programmed in one way or another to behave predictably according to the global application distributed on the cores. We started a collaboration on this topic with the "Embedded Systems-on-Chips" department of the LIP6 laboratory, one of the main site of expertise for SoC/NoC design and Hardware/software codesign. This collaboration first materialized with the co-supervision of M. Djemal's PhD thesis. A generic MPSoC architecture is being defined, which includes a 2D mesh network-on-chip with programmable routers, on which static routing schedules such as synthesized by our tools may be implemented and run.